Ultra-Small Chips
Carbon nanotubes may replace copper conductors as interconnects for silicon chips.
Research Task: The Integration of Nanostructured Materials into Practical Devices (ITSR/BN)
Principal Investigator: Jun Li, Ph.D., NASA Ames Research Center
In 1965, just four years after the first planar integrated circuit (IC) was discovered, Gordon Moore observed that the number of transistors per integrated circuit had since grown exponentially and predicted that it would continue to do so. The media soon labeled his prophesy "Moore’s Law," and for nearly forty years it has been validated by the technological progress achieved in the semiconductor industry. However, in the 2001 International Technology Roadmap for Semiconductors (ITRS), industry experts reported the presence of a potential "Red Brick Wall" that, as early as 2003, could block further scaling as predicted by Moore’s Law. The "red bricks" in the wall refer to those areas of technical challenge that are highlighted in red on the roadmap, indicating that there is no known manufacturable solution. A key "red brick’ is finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.
NASA is also keenly interested in the challenges of future chip development because of its need to develop smaller and more complex computer systems for future space missions. For this reason, Dr. Li's ITSR team is researching ways to integrate ultra-small nanostructured materials into practical devices such as silicon-based ICs. Li and his colleagues are combining lithography and other semiconductor processing techniques to build individual nanoelements such as carbon nanotubes (CNTs) and semiconducting nanowires (SNWs) into large-scale integrated devices from the bottom up. A major challenge they face is to develop new methods for linking nanostructured materials to macrosize practical units while maintaining the unique properties of the individual nanoelements.
In a significant breakthrough, Li and his colleagues recently reported a new bottom-up approach to integrating multiwalled carbon nanotubes (MWNTs) into multilevel interconnects for manufacturing silicon-based ICs. The team’s paper, "Bottom-up approach for carbon nanotube interconnects," was published as the cover story in the April 14, 2003 issue of Applied Physics Letters (Vol. 82, No. 15).
In the paper, Li’s team demonstrated "a material and processing solution to integrate carbon nanotubes into multileveled interconnects to meet future silicon IC needs. The process sequence—which involves lithography, metallization, plasma deposition of CNTs, dielectric gap–filling, planarization, annealing, etc.—is compatible with current IC manufacturing practice." They also note that, in this new process, the "MWNTs can be grown precisely at desired locations and retain their integrity; thus they are applicable for multilevel vertical interconnects." Electrical tests indicate that such MWNTs can carry current density as high as 106 A⁄cm2 for several days without notable degradation. This makes the MWNT the only material that meets the ITRS requirements for removing the "red brick" on interconnects.
To learn more about the breakthrough achieved by Dr. Li and his team, see the NASA Ames press release (4-14-2003): http://amesnews.arc.nasa.gov/releases/2003/03_26AR.html
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